A semiconductor memory device typically stores information via charges accumulated in cell capacitors. One such device that stores information in this manner is a Dynamic Random Access Memory (DRAM). Charges that accumulate in cell capacitors of a semiconductor memory device may dissipate over time through leakage. This charge leakage may lead to information loss unless refresh operations are periodically carried out. In a semiconductor memory device, such as a DRAM or the like, refresh operations are typically controlled through refresh commands. For example, a control device that controls the DRAM may periodically issue refresh commands that indicate refresh operations. The control device may issue the refresh commands at a frequency such that all word lines are refreshed at least once during the period of one refresh cycle. For example, with a 64 millisecond refresh cycle, a control device may issue a plurality of refresh commands that ensure every word line is refreshed at least once every 64 milliseconds.
The information retention characteristics of a memory cell may be reduced in some cases as a consequence of the access history of the memory cell. If the information retention time of the memory cell is reduced to less than one refresh cycle, part of the information stored in the memory cell may be lost even when refresh commands are issued at a frequency that refreshes all word lines at least one time per refresh cycle. Various factors may give rise to this problem in DRAMs. For example, cell leakage may occur due to crystal defects, foreign matters, etc., which may be present in memory cells by some degree. Cell leakage may also emerge due to interference from adjacent word tines or noise caused along with memory access. In some cases, the impact of access history on information retention may be mitigated by providing a disturb counter, which counts and/or stores the number of accesses that occur for each memory section. If an access count becomes larger than a predetermined threshold value, the refresh frequency of the section may be increased.
With miniaturization of DRAMs advancing to become a 2x-nm process in the current generation, the “row hammer” phenomenon has emerged. Generally, the “row hammer” phenomenon occurs when adjacent cell charges are lost by minor carriers that are generated every time a word line is activated/deactivated. Errors may occur as a result. The row hammer phenomenon is an additional mechanism for information retention loss and thus presents additional difficulties for the reliability of DRAMs. A row hammer threshold value generally refers to the number of memory access for a given word line that result in errors occurring in adjacent word lines. As process dimensions shrink, row hammer threshold values become smaller. In the 20-nm process generation, row hammer threshold values become 100,000 times or less. Because of this increasing problem, it is becoming difficult to maintain correct operations without dedicated circuit solutions in DRAM or some other solution on the memory side.
Some solutions to the row hammer problem expand the above-mentioned disturb counter to monitor each row address so to determine a row address (hammer address) at which the number accesses has reached the row hammer threshold value. Once the disturb counter registers a threshold number of accesses, adjacent word line(s) are subjected to additional refresh operations. However, because the memory space of a memory system is much bigger than a single DRAM, an extremely large scale circuit has to be mounted in order to analyze the history of access to such memory cells, and the cost thereof is not realistic. This is even more so in a large-scale system such as a server.
Other solutions focus on the fact that the appearance frequency of hammer addresses, as determined the row hammer threshold, inevitably increases as the upper limit of the number of times of row access (the number of Active commands) which can be executed in a refresh cycle decreases. Here, row addresses may be captured at random timing and at an appropriate frequency according to a probabilistic memory control. When random capture of row addresses is used, only additional refresh with respect to the adjacent word line thereof is carried out. Therefore, the circuit scale can be extremely reduced, and, according to the probability of hitting the hammer addresses, practically high reliability can be obtained.